The ARM Cortex A-53 SoC packs a total of four cores. At the time of writing, IMP OS only concerns itself with a single core, as it is often the case that an Operating System is written for a single core before being expanded to cope with the complexity of running across multiple cores simultaneously.

As such, on the understanding that when IMP OS is launched, potentially all cores are running, it is appropriate for IMP OS to identify and run itself only one the first core: other cores will specifically put themselves into a simple “infinite loop”, ensuring that these cores are safely “parked” for the time being.

In the ARM 64-bit code, the point at which the kernel starts up starts with code that initiates this process using code similar to the following:

    MRS      x0 , MPIDR_EL1
    MOV      x1 , #0xff       
    ANDS     x0 , x0 , x1       
    BEQ      _kernel_first_core_instruction       
    B        _kernel_parked_loop

As can be seen – in the 64-bit context – that the register responsible for identifying the specific core is checked, and only if it is identified as core #0 (the 1st core), is the kernel continued with. For all other cores, a simple loop is entered to prevent the core from actively taking part in the kernel.